Career
Overview..!!
I am Engineer shaping next-gen chips through VLSI design, computer architecture, and innovative semiconductor research.
With experience across VLSI and Computer Architecture engineering, I’ve built strong skills in understanding technical requirements and delivering solutions that align with modern semiconductor trends. I’ve worked on projects across RTL design, Verification, FPGA prototyping, Computer architecture and Device-level research, so you can rely on me for end-to-end hardware development.
I’ve contributed to designs that are already tested and validated, and I can provide practical suggestions, optimized design approaches, and multiple solution paths to choose from. With me, you’re never limited to one direction — I work collaboratively and adapt to what best fits your project or research goals.
Education
Aug 2023 – May 2025
The George Washington University
Washington DC, USA
Master of Science – Computer Engineering (GPA : 3.6 / 4)
Specialization: VLSI, Chip Fabrication & Computer Architecture
Sept 2018 – June 2022
Dayananda Sagar College of Engineering
Bangalore, India
Bachelor of Engineering – Electronics and Communication (CGPA : 3.15 / 4)
Course list: Digital Electronics, Analog Electronics, Nanoelectronics, Digital System Design using Verilog, Fundamentals of VLSI Design, ASIC Design, System Verilog for Verification
Area of Focus
Front End Domain :
RTL Design & Integration
FPGA / ASIC Design Verification
SoC Design Verification
System Architecture
Back End Domain :
Static timing analysis (STA)
Design For Testability (DFT)
Physical design
Custom layout Design
GDSII (Graphic design system) extraction
Micro & Nano Fabrication
Experience
Aug 2024 – May 2025
The George Washington University
Washington DC, USA
Student Lab Assistant
Assisted the Faculty, Research Staff at Electrical & Computer Engineering, carrying out experiments, projects and tests in the laboratories. Taught Analog Electronics and Circuit Design Lab for Undergraduate students
June 2024 – Aug 2024
Akkodis
King of Prussia, USA
Trainee Intern – FPGA Design and Verification
During my tenure as a Trainee Intern, I contributed to multiple custom FPGA design projects, where I performed UVM-based verification, utilized Cadence Innovus for implementation tasks, and generated coverage reports using QuestaSim. I also worked with Synopsys VCS for ATGP workflows. My time at Akkodis Academy and Siemens Xcelerator Academy provided extensive hands-on training, enabling me to strengthen my expertise in FPGA design and verification.
Feb 2022- Aug 2023
Maven Silicon
Bangalore, India
Trainee – Advanced VLSI Design & Verification
Excelled skills in the domains of DFT, FPGA Design, Static Timing Analysis & Verification Methodologies such as OVM, UVM and Assertion based Verification: System Verilog Assertions. Developed projects such as Router 1×3 and AHB2APB Bridge IP Core – Design & Verification.